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ADF5610 데이터시트(PDF) 42 Page - Analog Devices

부품명 ADF5610
상세설명  Microwave Wideband Synthesizer Integrated VCO
PDF  51 Pages
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ADF5610 데이터시트(HTML) 42 Page - Analog Devices

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ADF5610
Data Sheet
Rev. 0 | Page 42 of 51
Bit
Type
Name
Default
Description
6
Read/Write
LKD_ONESHOT_SEL
1
Lock detection window timer selection.
1: digital programmable timer.
0: analog one shot, nominal 10 ns window.
9:7
Read/Write
LKD_ONESHOT_DURATION
2
Lock detection, digital window duration.
0: half cycle.
1: one cycle.
2: two cycles.
3: four cycles.
4: eight cycles.
5: 16 cycles.
6: 32 cycles.
7: 64 cycles.
11:10
Read/Write
LKD_CONFIG
0
Lock detect digital timer frequency control (see the Lock Detect
section for more information).
00: fastest.
11: slowest.
12
Read/Write
Reserved
0
Reserved.
13
Read/Write
LKD_AUTOCAL_WHEN_UNLOCKED
0
1: autorelock attempts to relock one time, if lock detect fails for any
reason.
ANALOG ENABLE (EN) REGISTER
Table 25. Register 0x08, Analog EN Register (Default 0xC1BEFF)
Bit
Type
Name
Default
Description
0
Read/Write
BIAS_EN
1
Enables main chip bias reference.
1
Read/Write
CP_EN
1
Charge pump enable.
2
Read/Write
PD_EN
1
PD enable.
3
Read/Write
REFBUF_EN
1
Reference path buffer enable.
4
Read/Write
VCOBUF_EN
1
VCO path RF buffer enable.
5
Read/Write
GPO_PAD_EN
1
0: disables the SDO pin.
1: enables the GPO port or allows a shared SPI.
When Bit 5 = 1 and Register 0xF, Bit 7 = 1, the SDO pin is always driven, which is
required for use of the GPO port.
When Bit 5 = 1 and Register 0xF, Bit 7 = 0, SDO is off when an unmatched chip
address is seen on the SPI. Allows shared SPI with other compatible devices.
9:6
Read/Write
Reserved
11 decimal
(0x0B)
Reserved.
10
Read/Write
VCO_SIDE_BIAS
1
VCO buffer and prescaler bias enable.
18:11
Read/Write
Reserved
55 decimal
(0x37)
Reserved. Program to 55 decimal (0x37).
19
Read/Write
DIV_SEL
0
8 GHz divide by 2 enable. Allows PLL operation up to 8 GHz.
When input to PLL is less than 4000 MHz, set to 0 decimal to bypass internal
divider.
When input to PLL is greater than or equal to 4.0 GHz, set to 1 decimal to enable
internal fixed divide by 2.
20
Read/Write
Reserved
0
Reserved. Program 0.
21
Read/Write
HI_FREQ_RF_SEL
0
High frequency reference select. Program to 1 for reference frequencies from
200 MHz to 350 MHz. Program to 0 for reference frequencies less than 200 MHz.
23:22
Read/Write
Reserved
3 decimal
Reserved.



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