DP83848MPHPREP datasheet(9/97 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Pin Configuration and Functions

Table 3-5. LED Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

LED_LINK

S, O, PU

LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of

the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.

LED_SPEED

S, O, PU

SPEED LED: The LED is ON when device is in 100 Mbps and OFF when in 10 Mbps. Functionality of this LED is

independent of mode selected.

LED_ACT/COL

S, O, PU

ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or

Receive.

COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED

output may be programmed to indicate Full-duplex status instead of Collision.

Table 3-6. JTAG Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

TCK

I, PU

TEST CLOCK: This pin has a weak internal pullup.

TDI

I, PU

TEST DATA INPUT: This pin has a weak internal pullup.

TDO

TEST OUTPUT

TMS

I, PU

TEST MODE SELECT: This pin has a weak internal pullup.

TRST

I, PU

TEST RESET: Active low asynchronous test reset. This pin has a weak internal pullup.

Table 3-7. Reset and Power Down

TERMINAL

I/O

DESCRIPTION

NAME

NO.

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the DP83848-EP. Asserting this pin low for at least 1 µs

will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each

bit in Section 5.6. All strap options are re-initialized as well.

PWR_DOWN/INT

I, OD, PU

The default function of this pin is POWER DOWN.

POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a

Power Down mode.

INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition

occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister.

details on the interrupt mechanisms.

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