HM8563 datasheet(19/22 Pages) HMSEMI

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• 18 •

serial resistance

−−

parallel load capacitance

−

trimmer capacitance

Version B

−

Version C

−

CLKOUT output

δCLKOUT

CLKOUT duty factor

[1]

−

−%

I2 C-bus timing characteristics[2]

fSCL

SCL clock frequency

[3]

−−

400

kHz

tHD;STA

START condition hold time

0.6

−−

μs

tSU:STA

set-up time for a repeated

START condition

0.6

−−

μs

tLOW

SCL LOW time

1.3

−−

μs

tHIGH

SCL HIGH time

0.6

−−

μs

SCL and SDA rise time

−−

0.3

μs

SCL and SDA fall time

−−

0.3

μs

capacitive bus line load

−−

400

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−−

tSU:STO

set-up time for STOP condition

4.0

−−

μs

tSW

tolerable spike width on bus

−−

[1] Unspecified for fCLKOUT = 32.768 kHz.

[2] All timing values are valid within the operating supply voltage range at Tamb and referenced to VIL and

VIH with an input voltage swing of VSS to VDD.

[3] I

2C -bus access time between two STARTs or between a START and a STOP condition to this device

must be less than one second.

Fig 18 I2C -bus timing waveforms.

HM8563

HM8563 데이터시트(PDF) 19 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

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