TS4975

Application Information

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4.7

Startup time

When the TS4975 is controlled to switch to full standby (output mode 0) to another output

mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb

and Vcc values. A typical value can be calculated by following formula:

This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the

startup time will be always lower.

capacitor Cb.

Figure 62. Typical startup time versus bypass capacitance

4.8

Pop and click performance

The TS4975 has internal pop and click reduction circuitry which eliminates the output

transients, for example during switch-on or switch-off phases, during a switch from an output

mode to another or during change in volume. The performance of this circuitry is closely linked

to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended

configuration) and the bias voltage bypass capacitor Cb.

The value of Cin and Cout is determined by the the lower cut-off frequency value requested.

The value of Cb will affect the THD+N and PSRR values in lower frequencies.

The TS4975 is optimized to have a low pop and click in the typical schematic configuration (

t

wu

C

b

V

CC

V

CC

1.2

–

-------------------------

×

50000

0.008 s

()

+

×

=

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

0

50

100

150

200

250

300

350

400

Vcc=2.5V

Vcc=3.3V

Bypass capacitor Cb (

Vcc=5V