전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

WM8802SCFT 데이터시트(PDF) 13 Page - Wolfson Microelectronics plc

부품명 WM8802SCFT
상세설명  Digital Audio Interface Transceiver
PDF  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8802SCFT 데이터시트(HTML) 13 Page - Wolfson Microelectronics plc

Back Button WM8802SCFT Datasheet HTML 9Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 10Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 11Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 12Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 13Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 14Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 15Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 16Page - Wolfson Microelectronics plc WM8802SCFT Datasheet HTML 17Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 65 page
background image
Product Preview
WM8802
w
PP Rev 1.1 April 2004
13
DESCRIPTION OF DEMODULATION FUNCTION
The demodulation function operation settings are performed using RXOPR.
CLOCKS
PLL (LPF)
The VCO (Voltage Controlled Oscillator) can be stopped if PLLOPR is set. Synchronization to
frequencies from 32kHz to 192kHz and RMCK of 4MHz to 25MHz can be selected.
The PLL clock frequency is selected with PLLSEL. For systems with an input data sampling
frequency of 105kHz or lower, the initial setting of 512fs is recommended. Since the system clock
RMCK output initial value is set to 1/2 of PLLSEL, the RMCK output is 256fs when a PLL clock
frequency of 512fs is used.
For systems with an input data sampling frequency higher than 105kHz, the PLL clock frequency
should be set to 256fs. RMCK will be 128fs if PRSEL0 is set to 1 and the same initial output setting
(i.e. 256fs) is used,
LPF is a PLL loop filter pin. Resistances and capacitances should be selected in accordance with
the frequency of the PLLSEL system clock. The PLLSEL setting should be set prior to bi-phase data
input since PLLSEL switching involves a change in LPF loop filter constant.
C
1
C
0
R
0
LPF
Figure 5 Loop Filter Configuration
PLLCK1
PLLCK0
R0
C0
C1
0
0
0
1
150Ω
0.047µF
0.0068µF
1
0
1
1
220Ω
0.068µF
0.0047µF
Table 6 Loop Filter Component Values



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com