 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
WM8802SCFTV 데이터시트(PDF) 20 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8802SCFTV 데이터시트(HTML) 20 Page - Wolfson Microelectronics plc |
|
|
20 / 65 page  WM8802 Product Preview w PP Rev 1.1 April 2004 20 CLOCK SWITCH TRANSITION SIGNAL OUTPUT ( CKST ) CKST outputs Low when the output clock changes during PLL lock/unlock. In the lock-in stage (PLL locked following the detection of input data) the CKST Low pulse falls at the word clock edge generated from the XIN clock. The CKST Low pulse rises at the same timing as RERR following the lapse of a given period. In the unlock stage, the CKST Low pulse falls at the same timing as the PLL lock detection signal RERR and rises following a given number of word clocks generated from the XIN clock. The PLL lock status change and clock change timing is detected by the rising and falling edges of the CKST Low pulse. RERR RMCK VCO Clock XTAL Clock Locked status RX0 to RX6 (a) Lock-in stage 45 ms to 300 ms Same timing as RERR After PLL lock Digital Data Lock Unlock CKST RERR RMCK VCO Clock XTAL Clock Locked status RX0 to RX6 (b) Unlock stage Same timing as RERR Digital Data Unlock Lock CKST 0.6 ms to 6.4 ms Figure 8 Clock Switch Timing |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
