11-266
RF2958
Rev A0 050209
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
Digital Input
Specifications
Apply to pins: SSB, SDI, SCLK,
MODE0, MODE1
Input High Voltage (VIH)0.7VDD
V
Input Low Voltage (VIL)0.3VDD
V
Input High Static Current (IIH)5
µA
Input Low Static Current (IIL)5
µA
Reset Time
50
µs
Exiting Reset mode or using SPI Reset
Apply to pins: SSB, SDI, SCLK
Input Setup Time (TSU)*
5
ns
Input Hold Time (THLD)*
5
ns
Input Rise/Fall Time (TRFI)5
ns
Input Clock to Select Time (TCS)5
ns
Input Clock Pulse Width High
(TCWH)
22
ns
Input Clock Pulse Width Low
(TCWL)
22
ns
PLL Recalibration Pulse Width
(TRC)
1/fr
s
For fr=22MHz, TRC is 45.5ns minimum
Digital Driver Output
Apply to pin: SDI (output mode)
Output High Voltage (VOH)0.8VDD
V
With 1mA load
Output Low Voltage (VOL)0.2VDD
V
With 1mA load
Output Rise/Fall Time (TRFO)
5
ns
With 20pF maximum load capacitance mea-
sured from 10% to 90% of output voltage
Output Current Source (|IOH|)
3.8
mA
Output at (VDD-0.3V)
Output Current Sink (|IOL|)
10
mA
Output at 0.3V
MCLK Input (AC-Coupled)
MCLK can be driven DC-coupled by a
CMOS clock oscillator with rail-to-rail out-
puts. Other oscillator configurations may
require AC-coupling.
Apply to pin: MCLK
Peak-to-Peak Input Voltage
(VP-P)
500
mV
DC Bias at MCLK (MCLK_DC)
0.6
1.1
V
Specification Valid Range
Temperature
-30
+70
°C
Supply Voltage
2.7
3.0
3.6
V
Transmit Current
50
68
80
mA
MODE0=0, MODE1=1
Receive Current
30
52
60
mA
MODE0=1, MODE1=0
Idle Current
5
28
40
mA
MODE0=0, MODE1=0
Reset Current
1
2
mA
MODE0=1, MODE1=1
Hibernate Current
0.2
0.5
mA
*Setup and Hold Times are measured from the time where the waveforms cross VDD/2.
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