THS1009CDAR datasheet(21/31 Pages) TI

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THS1009

SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

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TIMING AND SIGNAL DESCRIPTION OF THE THS1009

The reading from the THS1009 and writing to the THS1009 is performed by using the chip select inputs (CS0, CS1),

the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This

is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two

chip select inputs can be used to interface easily to a processor.

Reading from the THS1009 takes place by an internal RDint signal, which is generated from the logical combination

of the external signals CS0, CS1 and RD (see Figure 28). This signal is then used to strobe out the words and to

enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active while

the write input (WR) is inactive. The first of those external signals switching to its inactive state deactivates RDint

again.

Writing to the THS1009 takes place by an internal WRint signal, which is generated from the logical combination of

the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and 1. The

last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input (RD) is

inactive. The first of those external signals going to its inactive state deactivates WRint again.

RDint

WRint

Control/Data

Registers

CS0

CS1

Data Bits

Figure 28. Logical Combination of CS0, CS1, RD, and WR

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