AM29DL640H55WHEN datasheet(10/54 Pages) AMD

10 / 54 page

Am29DL640H

February 9, 2005

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1.

Am29DL640H Device Bus Operations

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

IN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A21:A0 in word mode (BYTE# = V

IH), A21:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

3. If WP#/ACC = V

IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection

and Unprotection”. If WP#/ACC = V

HH, all sectors will be unprotected.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ15–DQ0 are active and controlled by

CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ14–DQ8 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH. The BYTE# pin deter mines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

Operation

CE#

OE#

WE#

RESET#

WP#/ACC

Addresses

(Note 2)

DQ15–DQ8

DQ7–

DQ0

BYTE#

= VIH

BYTE#

= VIL

Read

L/H

OUT

DQ14–DQ8 =

High-Z, DQ15 = A-1

OUT

Write

(Note 3)

Standby

VCC ±

0.3 V

VCC ±

0.3 V

L/H

High-Z

Output Disable

L/H

High-Z

Reset

L/H

High-Z

Sector Protect (Note 2)

L/H

SA, A6 = L,

A1 = H, A0 = L

Sector Unprotect (Note 2)

VID

(Note 3)

SA, A6 = H,

A1 = H, A0 = L

DIN

Temporary Sector

Unprotect

VID

(Note 3)

AIN

DIN

High-Z

DIN

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