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High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
7
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
Data Retention Mode
V
DR >= 1.5V
t
CDR
t
R
VIH
VIH
CE >= V
CC - 0.2V
Vcc
CE
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc/0V
WAVEFORMS
INPUTS
OUTPUTS
Input Rise and Fall Times
5ns
MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
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