FOR AUTOMOTIVE 105

°C OPERATION 2-WIRE SERIAL E

S-24CS01A/02A/04A H Series

16

7. 2 Random read

Random read is used to read the data at an arbitrary memory address.

A dummy write is performed to load the memory address into the address counter.

When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "0"

following a start condition, it responds with an acknowledge. The S-24CS01A/02A/04A then receives an 8-bit word

address and responds with an acknowledge.

The memory address is loaded to the address counter in the

S-24CS01A/02A/04A by these operations. Reception of write data does not follow in a dummy write whereas reception

of write data follows in a byte write and in a page write.

Since the memory address is loaded into the memory address counter by dummy write, the master device can read the

data starting from the arbitrary memory address by transmitting a new start condition and performing the same

operation in the current address read.

That is, when the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to

"1", following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the

S-24CS01A/02A/04A in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge ,

the reading of S-24CS01A/02A/04A is ended.

SDA

LINE

S

T

A

R

T

W

R

I

T

E

DEVICE

ADDRESS

WORD

ADDRESS (n)

M

S

B

DUMMY WRITE

S

T

A

R

T

R

E

A

D

DEVICE

ADDRESS

M

S

B

A

C

K

L

S

B

NO ACK from

Master Device

S

T

O

P

ADR INC

DATA

A

C

K

A

C

K

L

S

B

R

/

W

R

/

W

Remark1. A0 is P0 in the S-24CS04A.

2. W7 is optional in the S-24CS01A.

1 0 1 0 A2 A1 A0 0

W7 W6 W5 W4 W3 W2 W1 W0

1 0 1 0 A2 A1 A0 1

D7 D6 D5 D4 D3 D2 D1 D0

Figure 16 Random Read