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H5TQ2G43CFR-RDC 데이터시트(PDF) 21 Page - Hynix Semiconductor

부품명 H5TQ2G43CFR-RDC
상세설명  2Gb DDR3 SDRAM
PDF  33 Pages
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제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
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H5TQ2G43CFR-RDC 데이터시트(HTML) 21 Page - Hynix Semiconductor

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Rev. 1.0 / Apr. 2013
21
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Datab)
0
0
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
1D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
11
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
5D
1
0
0
0
0
0
00
0
0
F
0
-
6,7
D,D
11
1
1
0
0
00
0
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7



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