STM32MP157C datasheet(211/258 Pages) STMICROELECTRONICS

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DS12505 Rev 2

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STM32MP157C

Electrical characteristics

238

6.3.31

Compensation cell

6.3.32

Digital filter for sigma-delta modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 92 for DFSDM are derived from

tests performed under the ambient temperature, fpclkx frequency and VDD supply voltage

summarized in Table 13: General operating conditions, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5×VDD

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate

function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for

DFSDMx).

Table 91. Compensation cell characteristics

Symbol

Parameter

Condition

Min Typ Max Unit

ICOMPCELL

VDD current consumption

during code calculation

1.71 V ≤ VDD ≤ 2.7 V

3.5

2.7 V < VDD < 3.6 V

TREADY

Time needed for code

calculation

1.71 V ≤ VDD ≤ 2.7 V

300

µs

2.7 V < VDD < 3.6 V

250

Table 92. DFSDM measured timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM clock

1.71 V < VDD < 3.6 V

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 V < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

fCKOUT

Output clock

frequency

1.71 < VDD < 3.6 V

DuCyCKOUT

Output clock

frequency duty

cycle

1.71 < VDD < 3.6 V

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