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VSC8504-02 데이터시트(PDF) 12 Page - Microsemi Corporation

부품명 VSC8504-02
상세설명  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

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Revision History
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
1
1
Revision History
This section describes the changes that were implemented in this document. The changes are listed by
revision, starting with the most current publication.
1.1
Revision 4.2
Revision 4.2 of this datasheet was published in February 2019. In revision 4.2, VeriPHY descriptions
were updated and VeriPHY register information was deleted. For functional details of the VeriPHY suite
and the operating instructions, see the ENT-AN0125 PHY, Integrated PHY-Switch VeriPHY - Cable
Diagnostics application note.
1.2
Revision 4.1
Revision 4.1 was published in May 2018. The following is a summary of the changes in revision 4.1 of
this document.
•
Configuration procedure steps were clarified. For more information, see Configuration, page 41.
•
The description of bit 10 was updated for register 0. For more information, see Table 18, page 45.
•
Design considerations were updated. For more information, see Design Considerations, page 116.
1.3
Revision 4.0
Revision 4.0 was published in November 2017. The following is a summary of the changes in
revision 4.0 of this document.
•
A note was added about enhanced serial LED mode using the VDD LED drive state.
•
Details about LED pulsing were updated.
•
Information on enabling the serial clock was added.
•
Register bits were designated as “sticky” where appropriate.
•
A footnote was added about the fast link failure interrupt mask.
•
The default for the ring resiliency status bits 4:4 was updated from 00 to 11.
•
The default value for the MAC SerDes clause 37 advertised ability register was updated from
0x0000 to 0x01E0.
•
Footnotes regarding required register clears were added to the SIGDET/GPIO control register.
•
All GPIO input register bits marked as read-only and defaults updated.
•
Global interrupt status register defaults were added.
•
Register 30G changed from reserved to extended revision ID register.
•
Current consumption values were updated.
•
Some parameter names and conditions for recovered clock AC characteristics were updated.
•
Product SKUs in the package section were corrected to match the ordering information.
•
Design considerations were removed and new ones added to correctly reflect device functionality.
1.4
Revision 2.0
Revision 2.0 of this datasheet was published in September 2017. This was the first publication of the
document.



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