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VSC8504-02 데이터시트(PDF) 123 Page - Microsemi Corporation

부품명 VSC8504-02
상세설명  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8504-02 데이터시트(HTML) 123 Page - Microsemi Corporation

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Pin Descriptions
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
112
6.3.8
Twisted Pair Interface
The following table lists the twisted pair interface pins.
MDIO
N2
I/O, OD
Management data input/output pin. Serial data is written or read
from this pin bidirectionally between the PHY and Station Manager,
synchronously on the positive edge of MDC. One external pull-up
resistor is required at the Station Manager, and its value depends
on the MDC clock frequency and the total sum of the capacitive
loads from the MDIO pins.
NRESET M3
I, PD, ST, 3 V Device reset. Active low input that powers down the device and
sets all register bits to their default state.
Table 134 •
Twisted Pair Interface Pins
Name
Pin
Type
Description
TXVNA_0
TXVNA_1
TXVNA_2
TXVNA_3
B14
B10
B6
B2
ADIFF TX/RX channel A negative signal
TXVNB_0
TXVNB_1
TXVNB_2
TXVNB_3
B15
B11
B7
B3
ADIFF TX/RX channel B negative signal
TXVNC_0
TXVNC_1
TXVNC_2
TXVNC_3
C15
B12
B8
B4
ADIFF TX/RX channel C negative signal
TXVND_0
TXVND_1
TXVND_2
TXVND_3
D15
B13
B9
B5
ADIFF TX/RX channel D negative signal
TXVPA_0
TXVPA_1
TXVPA_2
TXVPA_3
A14
A10
A6
A2
ADIFF TX/RX channel A positive signal
TXVPB_0
TXVPB_1
TXVPB_2
TXVPB_3
A15
A11
A7
A3
ADIFF TX/RX channel B positive signal
TXVPC_0
TXVPC_1
TXVPC_2
TXVPC_3
C16
A12
A8
A4
ADIFF TX/RX channel C positive signal
TXVPD_0
TXVPD_1
TXVPD_2
TXVPD_3
D16
A13
A9
A5
ADIFF TX/RX channel D positive signal
Table 133 •
SMI Pins (continued)
Name
Pin
Type
Description



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