Variant

Membe

r Code

M20K

M10K

MLAB

Total RAM Bit

(Kb)

Block

RAM Bit

(Kb)

Block

RAM Bit

(Kb)

Block

RAM Bit

(Kb)

Arria V ST

D3

—

—

1,729

17,290

3223

2,014

19,304

D5

—

—

2,282

22,820

4253

2,658

25,478

Embedded Memory Configurations

Table 17: Supported Embedded Memory Block Configurations for Arria V Devices

This table lists the maximum configurations supported for the embedded memory blocks. The information is

applicable only to the single-port RAM and ROM modes.

Memory Block

Depth (bits)

Programmable Width

MLAB

32

x16, x18, or x20

x10

M20K

512

x40

1K

x20

2K

x10

4K

x5

8K

x2

16K

x1

M10K

256

x40 or x32

512

x20 or x16

1K

x10 or x8

2K

x5 or x4

4K

x2

8K

x1

Clock Networks and PLL Clock Sources

650 MHz Arria V devices have 16 global clock networks capable of up to operation. The clock network

architecture is based on Altera's global, quadrant, and peripheral clock structure. This clock structure is

supported by dedicated clock input pins and fractional PLLs.

Note: To reduce power consumption, the Quartus II software identifies all unused sections of the clock

network and powers them down.

(11)

Available for Arria V GZ devices only.

AV-51001

2015.01.23

Embedded Memory Configurations

21

Arria V Device Overview

Altera Corporation

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