NJU6673 datasheet(7/38 Pages) NJRC

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NJU6673

Ver.2003-04-08

TERMINAL DESCRIPTION

No.

Symbol

I/O

Function

21-

24,

33,

37,

38,

57,

76,

77,

79,

80,

97,

198,

210,

211

DUMMY1

DUMMY2

DUMMY3 -

DUMMY6

DUMMY7

DUMMY8

DUMMY9

DUMMY10

DUMMY11

DUMMY12

DUMMY13

DUMMY14

DUMMY15

DUMMY16

DUMMY17

DUMMY18

Dummy Terminal.

These are open terminals electrically.

4,5,6,

54-56

VDD

Power

Power supply terminal. (+2.4 to +5.5V)

9-11,

34-36

VSS

GND

Ground terminal. (0V)

LCD Driving Voltage Supplying Terminals.

In case of external power supply operation without internal power supply

operation, each level of LCD driving voltage is supplied from outside

fitting with following relation.

VDD

≥V

OUT

In case of internal power supply, LCD driving voltages V1 to V4

depending on the bias selection are supplied as shown in follows;

Duty

Bias

1/15 Duty

1/5 Bias V5+4/5 VLCD V5+3/5 VLCD V5+2/5 VLCD V5+1/5 VLCD

1/25 Duty

1/6 Bias V5+5/6 VLCD V5+4/6 VLCD V5+2/6 VLCD V5+1/6 VLCD

73-75

70-72

67-69

64-66

61-63

Power

VLCD=VDD-V5

39-41

42-44

45-47

48-50

C1+

C1-

C2+

C2-

Condenser connecting terminals for internal Voltage Booster.

Boosting time is selected by each connected condenser.

In case of 3-time boost operation, connect the condenser between C1+

and C1-, C2+ and C2-.

In case of 2-time boost operation, connect the condenser between C2+

and C2-, connect C2+ to C1+, and C1- should be open.

51-53

VOUT

Boosted voltage output terminal.

Connects the capacitor between VOUT

terminal and VSS.

58-60

VLCD voltage adjustment terminal.

The gain of VLCD setup circuit for V5

level is adjusted by external resistor.

LCD bias voltage control terminals.

Voltage

booster circuit

Voltage adjustor

V/F circuit

H/L

Available

Not available

Available

Not available

Available

T1,

D6(SCL)

D7(SI)

I/O

Data input / output terminals.

In parallel interface Mode (P/S=”H”)

I/O terminals of 8-bit bus.

In Serial interface Mode(P/S=”L”)

D7:Input terminal of serial data (SI).

D6:Input terminal of serial data clock (SCL).

D5 to D0 terminals are High impedance.

When CS=”H” , D0 to D7 terminals are high-impedance.

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