DDR memory. Visual Trigger used to isolate a rare occurrence of a write burst on a

specific bit pattern in DDR3. The trigger event is a Write DQ burst of 11000000, when the

DQ launch starts from a non-tri-state voltage value. DDR memory bus events involve

clocks, strobes and data channels as well as multiple amplitudes and bursts of data.

Boolean logic trigger qualification. Boolean logic using logical OR allows the user to

simultaneously monitor each bit and capture the occurrence of an anomaly at any point

in the acquisition.

Trigger on the width of a burst of 10 pulses. By drawing a "Must be outside" area before

the first clock pulse and a second "Must be outside" area after the tenth pulse, as shown,

you can define a Visual Trigger setup that captures the desired burst width.

Serial triggering and analysis (optional)

On a serial bus, a single signal often includes address, control, data, and

clock information. This can make isolating events of interest difficult. The

DPO7000C Series offers a robust set of tools for debugging serial buses

RS-232/422/485/UART, MIL-STD-1553, and USB 2.0, and decode for MIPI

D-PHY DSI-1 and CSI-2, 8b/10b, Ethernet, and PCI Express serial buses.

Serial triggering

Trigger on packet content such as start of packet, specific addresses,

specific data content, unique identifiers, etc. on popular serial interfaces

STD-1553, and USB 2.0.

Datasheet

6 www.tek.com/DPO7000