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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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68HC05JB3 데이터시트(PDF) 15 Page - Freescale Semiconductor, Inc |
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68HC05JB3 데이터시트(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 134 page  November 5, 1998 GENERAL RELEASE SPECIFICATION MC68HC05JB3 GENERAL DESCRIPTION MOTOROLA REV 1 1-3 Figure 1-1. MC68HC05JB3 Block Diagram 144 Bytes RAM 2560 Bytes EPROM Low Speed USB 16-bit Timer Core TImer OSC ÷2 RESET and IRQ LVR VREF POWER SUPPLY CPU CONTROL ALU 68HC05 CPU ACCUM INDEX REG. CPU REGISTERS PROGRAM COUNTER COND CODE REG. 0 0 0 0 000 11 STK PNTR 0 111H I N Z C PA0x PA1x PA2x PA3x PA4y PA5y PA6y PA7y VDD VSS 3.3V RESET IRQ TCAP D+ D– OSC1 OSC2 y: 8mA current sink capability and optical interface : 25mA current sink, open-drained x: External edge interrupt capability, with internal pull-up, slow transition O/P : PB0 is shared with TCAP with Schmitt trigger input and optical interface PB0 PB1 PB2 PB4 PB5 PB6 PB7 PC0 † PC1 PC2 PC3 : Pins available in 28-pin package only †: PC0 shared with OCMP OCMP † Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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