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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HPC-DEV-WDBC 데이터시트(PDF) 7 Page - National Semiconductor (TI) |
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HPC-DEV-WDBC 데이터시트(HTML) 7 Page - National Semiconductor (TI) |
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7 / 30 page  Timing Waveforms (Continued) Timing Diagrams for TX Using External Enable TLDD10422 – 12 Symbol Parameter Min Max Units TETE Hold of TEN Low after HCK Rising Edge 5 ns TLTE Setup of TEN Rising Edge before HCK Rising Edge 85 ns TVTE Delay of TX Output Valid after TEN Rising Edge 40 ns TVTC Delay of TX Output Valid after HCK Rising Edge 65 ns THTE Hold of TEN High after HCK Falling Edge 60 ns TSTE Setup of TEN Falling Edge before HCK Falling Edge 20 ns TTTE Delay of TX Output TRI-STATE after TEN Falling Edge 40 ns TVTR TVTC in Rate Adaptation Mode 75 ns Timing Diagrams for RX Using External Enable TLDD10422 – 13 Symbol Parameter Min Max Units TERE Hold of REN Low after HCK Rising Edge 5 ns TLRE Setup of REN Rising Edge before HCK Falling Edge 30 ns TVRS Setup of RX Data Input Valid before HCK Falling Edge 20 ns TVRH Hold of RX Data Input Valid after HCK Falling Edge 20 ns THRE Hold of REN High after HCK Rising Edge 5 ns TSRE Setup of REN Falling Edge before HCK Falling Edge 30 ns 7 |
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