AM93LC86

16384-bits Serial Electrically Erasable PROM

(Preliminary)

Anachip Corp.

www.anachip.com.tw

Rev 0.1 Oct 20, 2003

6/12

Timing Diagrams

Organization Key

AM93LC86 (16K)

I/O

X8

X16

Figure 2. Synchronous data timing

T

t

SKH

t

SKL

t

CSH

t

CSS

CS

SK

DI

DO(READ)

DO(WRITE)

(WRALL)

(ERASE)

(ERALL)

t

SV

STATUS VALID

t

DF

t

DF

t

PD1

t

PDO

t

DIS

t

DIH

Figure 3. Data read cycle timing

CS

SK

+

AO

AN

0

1

1

DI

DN

DO

O

DO

TRI-STATE

+For all instructions, SK cycles before start bit don't care.

*Address Pointer Cycle to the Next Register.

*

t

CS