A67L93181/A67L83361

Preliminary

512K X 18, 256K X 36 LVTTL, Flow-through ZeBL

PRELIMINARY

(July, 2005, Version 0.0)

2

AMIC Technology, Corp.

Features

Fast access time: 6.5/7.5/8.5 ns

(153, 133, 117 MHz)

Zero Bus Latency between READ and WRITE cycles

allows 100% bus utilization

Signal +3.3V

± 5% power supply

Individual Byte Write control capability

operations

Clock-controlled and registered address, data and

control signals

Registered output for pipelined applications

Three separate chip enables allow wide range of options

for CE control, address pipelining

Internally self-timed write cycle

Selectable BURST mode (Linear or Interleaved)

SLEEP mode (ZZ pin) provided

Available in 100 pin LQFP package

General Description

The AMIC Zero Bus Latency (ZeBL

employs high-speed, low-power CMOS designs using an

advanced CMOS process.

The A67L93181, A67L83361 SRAMs integrate a 512K X

18, 256K X 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. These SRAMs

are optimized for 100 percent bus utilization without the

insertion of any wait cycles during Write-Read alternation.

The positive edge triggered single clock input (CLK)

controls

all

synchronous

inputs

passing

through

the

registers. The synchronous inputs include all address, all

(R/

(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst

mode (MODE). Burst Mode can provide either interleaved

or linear operation, burst operation can be initiated by

synchronous address Advance/Load (ADV/LD ) pin in Low

state.

Subsequent

burst

address

can

be

internally

generated by the chip and controlled by the same input pin

ADV/LD in High state.

Write cycles are internally self-time and synchronous with

The feature simplified the write interface. Individual Byte

defined when an address is loaded.

The SRAM operates from a +3.3V power supply, and all

inputs and outputs are LVTTL-compatible. The device is

ideally suited for high bandwidth utilization systems.