EVAL-ADE7763EB datasheet(9/56 Pages) AD

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ADE7763

Rev. A | Page 9 of 56

Pin No.

Mnemonic

Description

CLKIN

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.

Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock

source for the ADE7763. The clock frequency for specified operation is 3.579545 MHz. Ceramic load

capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal

manufacturer’s data sheet for load capacitance requirements.

CLKOUT

A crystal can be connected across this pin and CLKIN, as described for Pin 15, to provide a clock source for

the ADE7763. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN

or a crystal is being used.

Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7763 to share

the serial bus with several other devices—see the Serial Interface section.

SCLK

Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this

clock—see the Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source

that has a slow edge transition time, such as an opto-isolator output.

DOUT

Data Output for the Serial Interface. Data is shifted out at this pin upon the rising edge of SCLK. This logic

output is normally in a high impedance state, unless it is driving data onto the serial data bus—see the

Serial Interface section.

DIN

Data Input for the Serial Interface. Data is shifted in at this pin upon the falling edge of SCLK—see the

Serial Interface section.

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