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MTC20136

Memory map modes

Three modes are defined :

a) Normal mode:

The internal RAM is mapped in the lower part of memory. This is the normal operating mode, it allows

maximum speed access to exception vectors.

b) Normal boot mode:

If the TROM external pin is high at reset, the MTC20136 boots from an external FEPROM.

c) Internal boot mode:

If the TROM external pin is low at reset, the MTC20136 boots from its internal ROM. This mode can be

used to perform code download from a host.

Boot modes are used at RESET time.

Boot_M0 andBoot_M1 on pin 26 and 27 conrol the port to be used for downloading the code into the

SDRAM after Bootup. This when TROM is low.

MTC20135, MTC20455 access

The MTC20136 directly connects to the MTC20135 without glue logic. Following features are provided for

MTC20135 access :

– 16 bit multiplexed address/data bus giving 64Kbyte address space per MTC20135.

– synchronous ready-controlled operation - control signals : nCS[4:7], E_CLK, ALE, W/nR, nRDYRCV

– Little endian byte ordering on 16 bit bus - nRDYRCV timeout mechanism

The timing diagram of the access to the MTC20135 or MTC20455 is shown in figure 3:

Pin Name

MTC20135, MTC20455

access function

SDRAM

access function

SRAM/FEPROM

access function

E_A [15:0]

-

S_A [11:0]

E_A [15:0]

E_D [15:0]

AD [15:0]

S_Q [15:0]

E_D [15:0]

E_nCS [1:0]

-

-

E_nCS [1:0]

E_nCS [7:4]

nCS [7:4]

-

-

E_nCS_S

-

S_nCS

-

E_Clk

E-Clk

S_Clk

-

E_ALE

ALE

-

-

E_nRDYRCV

nRDYRCV

-

-

E_nOE

-

-

E_nOE

E_nWE0

W/nR

-

E_nWE0

E_nWE1

-

S_nWE

E_nWE1

Boot_M1

(Pin27)

Boot_M0

(Pin26)

0

1

9600 Bps via serail port 1

1

0

Par. CTRL-E

1

1

Par.CTRL-E

Table 1. (continued)