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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP8418 데이터시트(PDF) 21 Page - National Semiconductor (TI) |
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DP8418 데이터시트(HTML) 21 Page - National Semiconductor (TI) |
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21 / 28 page  Electrical Characteristics VCC e 50V g10% 0 C s TA s 70 C unless otherwise noted (Note 2) Symbol Parameter Conditions Min Typ Max Units VC Input Clamp Voltage VCC e Min IC eb 12 mA b 08 b 12 V IIH Input High Current for all Inputs VIN e 25V 20 100 m A II RSI Output Load Current for RFIO VIN e 05V Output high b 07 b 15 mA IIL1 Input Low Current for all Inputs VIN e 05V b 002 b 025 mA IIL2 ADS RC CS M2 RASIN VIN e 05V b 005 b 05 mA VIL Input Low Threshold 08 V VIH Input High Threshold 20 V VOL1 Output Low Voltage IOL e 20 mA 03 05 V VOL2 Output Low Voltage for RFIO IOL e 8 mA 03 05 V VOH1 Output High Voltage IOH eb 1 mA 24 35 V VOH2 Output High Voltage for RFIO IOH eb 100 mA 24 35 V I1D Output High Drive Current VOUT e 08V (Note 3) b 50 b 200 mA I0D Output Low Drive Current VOUT e 24V (Note 3) 50 200 mA ICC Supply Current VCC e Max 150 240 mA Except RFIO Except RFIO ADS RC CS M2 RASIN Switching Characteristics DP8417 DP8418 DP8419 DP8419X VCC e 50V g10% 0 C s TA s 70 C unless otherwise noted (Notes 2 4 5) the output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0-Q8 CL e 500 pF RAS0–RAS3 CL e 150 pF WE CL e 500 pF CAS CL e 600 pF RL e 500X unless otherwise noted See Figure 11a for test load S1 is open unless otherwise noted Maximum propagation delays are specified with all outputs switching Preliminary Symbol Parameter Condition CL All CL e 50 pF Units Min Max Min Max ACCESS tRICL0 RASIN to CAS Low Delay Figure 6 57 97 42 85 ns (RAHS e 0) DP8417 18 19-80 tRICL0 RASIN to CAS Low Delay Figure 6 57 87 42 75 ns (RAHS e 0) DP8417 18 19-70 tRICL1 RASIN to CAS Low Delay Figure 6 48 80 35 68 ns (RAHS e 1) DP8417 18 19-80 tRICL1 RASIN to CAS Low Delay Figure 6 48 70 35 58 ns (RAHS e 1) DP8417 18 19-70 tRICH RASIN to CAS High Delay Figure 6 37 ns tRCDL0 RAS to CAS Low Delay Figure 6 43 80 ns (RAHS e 0) DP8417 18 19-80 tRCDL0 RAS to CAS Low Delay Figure 6 43 72 ns (RAHS e 0) DP8417 18 19-70 tRCDL1 RAS to CAS Low Delay Figure 6 34 63 ns (RAHS e 1) DP8417 18 19-80 tRCDL1 RAS to CAS Low Delay Figure 6 34 55 ns (RAHS e 1) DP8417 18 19-70 tRCDH RAS to CAS High Delay Figure 6 22 ns tRAH0 Row Address Hold Time Figure 6 25 25 ns (RAHS e 0 Mode 5) tRAH1 Row Address Hold Time Figure 6 15 15 ns (RAHS e 1 Mode 5) tASC Column Address Set-up Time Figure 6 00 ns (Mode 5) 21 |
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