CS42L51 datasheet(21/83 Pages) CIRRUS

21 / 83 page

DS679A2

CS42L51

Notes:

15. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are set-

tled.

16. See “Example System Clock Frequencies” on page 75 for typical MCLK frequencies.

17. See “Master” on page 38.

Master Mode (Note 17)

Output Sample Rate (LRCK)

All Speed Modes

-Hz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

SCLK Rising Edge to SDOUT Output Delay

-s

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-40

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Parameters

Symbol

Min

Max

Units

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(LK-SK)

ts(SDO-SK)

Figure 4. Serial Audio Interface Slave Mode Timing

MCLK

128

-----------------

MCLK

-----------------

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(SDO-SK)

Figure 6. Serial Audio Interface Master Mode Timing

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