CS4922 datasheet(19/34 Pages) CIRRUS

19 / 34 page

CS4922

If the CS4922 fails to ACK it is possible that the

byte was rejected and it should be transmitted

again. If the second attempt fails the CS4922

should be issued a hardware reset to reinitialize the

communication path.

If the DSP core of the CS4922 wants to send a byte

to the master, it first writes the byte to the Serial

Control Port Output (SCPOUT) register. A write to

the SCPOUT sets the request pin (REQ) active low.

The master must recognize the request and issue a

read operation to the DSP. Figure 14 shows the rel-

ative timing of a single byte read. The master must

send the 7 bit address (if address checking is en-

abled it must match the address in the SCPCN reg-

ister) and the read bit. For I2C protocol, it is always

the device receiving the transfer that must ACK.

Therefore, the CS4922 will ACK the address and

the read bit. After the ACK by the CS4922 (the fall-

ing edge of SCL/SCK), the serial shift register is

loaded with the byte to be sent and the most signif-

icant bit is placed on the SDA line.

The 8 bit value in the serial shift register is shifted

out by the master. The data is valid on the rising

edge of SCL/SCK and transitions immediately fol-

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W

ACK

SDA

SCL/SCK

SDA

SCL/SCK

Start

Stop

Figure 12. Control Port Timing, I2C® Write

STATE

MACHINE

OUTPUT

CONTROL

INTERRUPT

CONTROL

SCPOUT

SCPIN

INT

I/O DATA

BUS

SREG

SCPCN

REQ

SCK/SCL

CDIN

SDA/

CDOUT

Figure 13. Serial Control Port

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