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CS5550 데이터시트(PDF) 16 Page - Cirrus Logic

부품명 CS5550
상세설명  Two-channel, Low-cost A/D Converter
PDF  24 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5550 데이터시트(HTML) 16 Page - Cirrus Logic

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CS5550
16
DS630F1
4.1.4 Power-Up/Halt
If the device is powered-down, this command will power-up the device. When powered-on, no computations will be
running. If the part is already powered-on, all computations will be halted.
4.1.5 Power-Down and Software Reset
The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the
analog/digital clock generators is turned off. In the sleep state, all circuitry except the digital clock generator and the
instruction decoder is turned off. Waking up the CS5550 out of sleep state requires more time than out of stand-by
state, because of the extra time needed to re-start and re-stabilize the analog clock signal.
S1,S0
Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This state allows quick power-on time
10 = Halt and enter sleep power saving state. This state requires a slow power-on time
11 = Reserved
4.1.6 Calibration
The device has the capability of performing a system offset calibration and gain calibration. Offset and gain calibra-
tions should NOT be performed at the same time (must do one after the other). Proper inputs must be supplied to
the device before initiating calibration.
A2,A1
Designates calibration channel
00 = Not allowed
01 = Calibrate the AIN1 channel
10 = Calibrate the AIN2 channel
11 = Calibrate AIN1 channel and AIN2 channel simultaneously
G
Designates gain calibration
0 = Normal operation
1 = Perform gain calibration
O
Designates offset calibration
0 = Normal operation
1 = Perform offset calibration
B7
B6
B5
B4
B3
B2
B1
B0
10100000
B7
B6
B5
B4
B3
B2
B1
B0
100
S1
S0
000
B7
B6
B5
B4
B3
B2
B1
B0
1
1
0
A2
A1
0
G
O



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