CS61583 datasheet(28/44 Pages) CIRRUS

28 / 44 page

LOS1, LOS2 : Loss of Signal (PLCC pins 16, 53; TQFP pins 7, 42)

The LOS indication goes high when 175

± 15 consecutive zeros are received on the line

interface. The LOS indication returns low when a minimum 12.5% ones density signal over

175

± 75 bit periods with no more than 100 consecutive zeros is received.

Test

J-TCK : JTAG Test Clock (PLCC pin 51; TQFP pin 40)

Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped

low, all JTAG registers remain unchanged.

J-TMS : JTAG Test Mode Select (PLCC pin 50; TQFP pin 39)

An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up

resistor.

J-TDI : JTAG Test Data In (PLCC pin 19; TQFP pin 10)

JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data

must be stable on the rising edge of J-TCK.

J-TDO : JTAG Test Data Out (PLCC pin 17; TQFP pin 8)

JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is

in progress. J-TDO will be updated on the falling edge of J-TCK.

CS61583

DS172PP5

CS61583 데이터시트(PDF) 28 Page - Cirrus Logic