L4989

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The reset circuit monitors the output voltage Vo. If the output voltage stays lower than Vo_th for filter time

trr, then Res goes low. If the output voltage Vo becomes lower than 2.0V (typ) than Res goes immediately

low. The reset low signal is guaranteed for an output voltage Vo greater than 1V.

When the output voltage goes back higher than Vo_th then Res goes high with a delay trd. This delay is

obtained by 512 period of an oscillator. The oscillator period is given by:

trd is given by

trd = 512 x Tosc

where:

Icr = 15

µA is an internally generated charge current,

Idr = 15

µA is an internally generated discharge current,

Vrhth=2.35V and Vrlth=0.65V are two typ thresholds,

Ctr is an external capacitance.

The Reset is always active and not depending on the state of WEn input pin.

Figure 2. Reset Time Diagram

Watchdog

The watchdog input Wi monitors a connected microcontroller. If pulses are missing, the Reset output

Res is set to low. The pulse sequence time can be set within a wide range with the external capacitor Ctw.

The watchdog circuit discharges the capacitor Ctw with the con-stant current Icwd. If the lower threshold

Vwlth is reached, a watchdog reset is generated.

To prevent this reset the microcontroller must generate a positive edge during the discharge of the capac-

which the microcontroller must output the positive edge the fol-lowing equation can be used

Every Wi positive edge switches the current source from discharging to charging, the same happens when

the lower threshold is reached. When the voltage reaches the upper threshold Vwhth the current switches

from charging to discharging. The result is a saw toothwaveform at the watchdog timer capacitor Ctw.

The Watchdog operation is active only if WEn input pin is set to logic state high.

T

osc

V

rht h

V

rl th

–

() Ctr

⋅

Icr

-------------------------------------------------

V

rht h

V

rl th

–

() Ctr

⋅

Id

-------------------------------------------------

+

=

trr

< trr

trd = 512 Tosc

Tosc

Vrhth

Vrlth

Res

Vcr

Vo

Wi

Vout_th

trr

< trr

trd = 512 Tosc

Tosc

Vrhth

Vrlth

Res

Vcr

Vo

Wi

Vout_th