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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BQ28Z610-R1 데이터시트(PDF) 11 Page - Texas Instruments |
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BQ28Z610-R1 데이터시트(HTML) 11 Page - Texas Instruments |
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11 / 32 page  11 BQ28Z610-R1 www.ti.com SLUSE07 – JANUARY 2020 Product Folder Links: BQ28Z610-R1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 7.25 N-CH FET Drive (CHG, DSG) Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V to 7.6 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Output voltage ratio RatioDSG = (VDSG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10 MΩ between PACK and DSG 2.133 2.333 2.467 — RatioCHG = (VCHG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10 MΩ between BAT and CHG 2.133 2.333 2.467 V(FETON) Output voltage, CHG and DSG on VDSG(ON) = VDSG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ between PACK and DSG 8.75 9.5 10.25 V VCHG(ON) = VCHG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ between VC2 and CHG 8.75 9.5 10.25 V(FETOFF) Output voltage, CHG and DSG off VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and DSG –0.4 0.4 V VCHG(OFF) = VCHG – VBAT, 10 MΩ between VC2 and CHG –0.4 0.4 tR Rise time VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG 200 500 µs VCHG from 0% to 35% VCHG(ON)(TYP), VVC2 ≥ 2.2 V, CL = 4.7 nF between CHG and VC2, 5.1 kΩ between CHG and CL, 10 MΩ between VC2 and CHG 200 500 tF Fall time VDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG 40 300 µs VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF between CHG and VC2, 5.1 kΩ between CHG and CL, 10 MΩ between VC2 and CHG 40 200 7.26 I 2C Interface I/O Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V to 7.6 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT VIH Input voltage high SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes) 0.7 × VREG V VIL Input voltage low SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes) –0.5 0.3 × VREG V VOL Output low voltage SCL, SDA, VREG = 1.8 V, IOL = 1 mA (FAST mode) 0.2 × VREG V SCL, SDA, VREG > 2.0 V, IOL = 1 mA (STANDARD and FAST modes) 0.4 V CIN Input capacitance 10 pF ILKG Input leakage current 1 µA RPD Pull-down resistance 3.3 kΩ 7.27 I 2C Interface Timing Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V to 7.6 V (unless otherwise noted) PARAMETER TEST CONDITION MIN NOM MAX UNIT tR Clock rise time 10% to 90% 300 ns tF Clock fall time 90% to 10% 300 ns tHIGH Clock high period 600 ns tLOW Clock low period 1.3 µs tSU(START) Repeated start setup time 600 ns td(START) Start for first falling edge to SCL 600 ns tSU(DATA) Data setup time 100 ns |
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