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STV82X7 데이터시트(PDF) 56 Page - STMicroelectronics |
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STV82X7 데이터시트(HTML) 56 Page - STMicroelectronics |
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56 / 149 page ![]() Register List STV82x7 56/149 I2S_CTRL I2S Synchronization Control Register I2S_STAT I²S Synchronization Status Register I2S_SYNC_OFFSET I²S Synchronization Offset Frequency Register 12.3 Clocking 1 A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the frequency recommended for reducing potential RF interference in the application. However, if Address: 04h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0000 LR_OFF LOCK_FLAG Bit Name Reset Function Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 05h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0000 LR_OFF LOCK_FLAG Bit Name Reset Function Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output Address: 06h Type: R/W |
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