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SC16C752 데이터시트(PDF) 13 Page - NXP Semiconductors |
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SC16C752 데이터시트(HTML) 13 Page - NXP Semiconductors |
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13 / 47 page ![]() Philips Semiconductors SC16C752 Dual UART with 64-byte FIFO Product data Rev. 04 — 20 June 2003 13 of 47 9397 750 11635 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see if any interrupt needs to be serviced. Figure 7 shows interrupt mode operation. 6.5.2 Polled mode operation In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 8 shows FIFO polled mode operation. Fig 7. Interrupt mode operation. 11 11 IIR IER THR RHR PROCESSOR IOW / IOR INT 002aaa230 Fig 8. FIFO polled mode operation. 00 00 LSR IER THR RHR PROCESSOR IOW / IOR 002aaa231 |
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