Sym

Parameter

Conditions

Min.

Typ.

Max.

Unit

XOUT capacitance

12

pF

IC-to-IC frequency variation (1) (2)

–10

+10

ppm

1. Devices in LCC8 package ((M41T62LC6F) are tested not to exceed ±20 ppm oscillator frequency error at

25 °C, which equates to about 52 seconds per month.

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P

Sym

Parameter (1)

Min.

Max.

Units

SCL clock frequency

0

400

kHz

Clock low period

1.3

µs

Clock high period

600

ns

SDA and SCL rise time

300

ns

SDA and SCL fall time

300

ns

START condition hold time

(after this period the first clock pulse is generated)

600

ns

START condition setup time

(only relevant for a repeated start condition)

600

ns

Data set-up time

100

ns

Data hold time

0

µs

STOP condition setup time

600

ns

Time the bus must be free before a new

transmission can start

1.3

µs

Watchdog output pulse width

96

98

ms

2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling edge of SCL.

M41T62, M41T64, M41T65

DC and AC parameters

DS3840 - Rev 24

page 26/42