TLF10180

February 1992

DM74LS197 Presettable Binary Counters

General Description

The ’LS197 ripple counter contains divide-by-two and di-

vide-by-eight sections which can be combined to form a

modulo-16 binary counter State changes are initiated by

the falling edge of the clock The ’LS197 has a Master Re-

set (MR) input which overrides all other inputs and asyn-

chronously forces all outputs LOW A Parallel Load input

(PL) overrides clocked operations and asynchronously

flops This preset feature makes the circuit usable as a pro-

grammable counter The circuit can also be used as a 4-bit

latch loading data from the Parallel Data inputs when PL is

LOW and storing the data when PL is HIGH For detail spec-

ifications and functional description please refer to the

’LS196 data sheet

Features

Y

High counting ratesTypically 70 MHz

Y

Asynchronous preset

Y

Asynchronous master reset

Connection Diagram

Dual-In-Line Package

TLF10180 – 1

Order Number DM74LS197M or DM74LS197N

See NS Package Number M14A or N14A

Pin Names

Description

CP0

d

2 Section Clock Input

(Active Falling Edge)

CP1

d

8 Section Clock Input

(Active Falling Edge)

MR

Asynchronous Master Reset Input

(Active LOW)

P0 – P3

Parallel Data Inputs

PL

Asynchronous Parallel Load Input

(Active LOW)

Q0

d

2 Section Output

Q1–Q3

d

8 Section Outputs

Q0 output is guaranteed to drive the full rated fan-out plus the CP1 input

Mode Select Table

Inputs

Response

MR

PL

CP

L

X

X

Qn Forced LOW

HL

X

Pn

HH

K

Count Up

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A