ST8500 datasheet(15/37 Pages) STMICROELECTRONICS

부품명	ST8500

상세설명	Programmable power line communication modem System on Chip

PDF	37 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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DocID031029 Rev 3

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ST8500

Device architecture

2.5

Clock and reset management (CRM)

2.5.1

Clock management

ST8500 internal clock signals can be generated from two different clock sources:

An external 25 MHz that must be provided through a crystal connected to MCLK_IN

and MCLK_OUT pins. If this source is not present the device does not start in order to

respect the security requirements.

An internal ring oscillator with 4 MHz nominal frequency.

The clock strategy and distribution is depicted in Figure 3.

Figure 3. ST8500 clock tree

At the power-on the Cortex™-M4F directly uses the XOSC clock with the SLOW mode. The

internal frequency synthesizer (FS) and pre-scaler units generate all the needed internal

clock signals. The frequency synthesizer generates a fixed frequency at a nominal

frequency of 400 MHz (VCO). This frequency is pre-scaled at boot time to provide the

proper clock for DFE, AFE and RTE subsystems.

ST8500 데이터시트(PDF) 15 Page - STMicroelectronics