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LCD-TFT (LTDC) display controller description

AN4861

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DocID029237 Rev 2

LCD-TFT (LTDC) display controller description

The LTDC is a controller that reads the data of images in a line per line fashion. Its memory

access mode is 64 bytes length, but when the end of a line is reached and less than

64 bytes are left, the LTDC fetches the remaining data.

3.1

Functional description

On every pixel clock-raising edge or clock-falling edge and within the screen active area, the

LTDC layer retrieves one pixel data from its FIFO, converts it to the internal ARGB8888 pixel

format and blends it with the background and / or with the other layer pixel color. The

resulting pixel, coded in the RGB888 format, goes through the dithering unit and is driven

into the RGB interface. The pixel is then displayed on the screen.

Figure 11. LTDC Block digram

3.1.1

LTDC clock domains

The LCD-TFT controller peripheral uses three clock domains:

•

AHB clock domain (HCLK): used to transfer data from the memories to the FIFO layer

and the other way around.

•

APB clock domain (PCLK): used to access the configuration and status registers.

•

The pixel clock domain (LCD_CLK): used to generate the LCD-TFT interface signals.

The LCD_CLK output should be configured following the panel requirements through

the PLL.

3.1.2

LTDC reset

The LTDC is reset by setting the LTDCRST bit in the RCC_APB2RSTR register.

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