SSL4120T

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© NXP B.V. 2012. All rights reserved.

Objective data sheet

Rev. 1 — 21 June 2012

39 of 47

NXP Semiconductors

SSL4120T

Resonant power supply control IC with PFC

[1]

The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of

the levels themselves.

[2]

Switching level has some hysteresis. The hysteresis falls within the limits.

[3]

For a typical application with a compensation network on pin COMPPFC, like the example in Figure 19.

[4]

Minimum required voltage change time for valley recognition on pin SNSAUXPFC.

[5]

Minimum time required between demagnetization detection and

ΔV/Δt = 0 on pin SNSAUXPFC.

HBC overcurrent protection voltage

positive level;

HS on + HS-LS non-overlap

time

0.9

1

1.1

V

negative level;

LS on + LS-HS non-overlap

time

−1.1

−1

−0.9

V

maximum boost compensation

current on pin SNSCURHBC

source current;

−0.5 V

-

−170 -

μA

sink current;

-

170

-

μA

HBC Capacitive Mode Protection (CMP) (pin HB)

time-out capacitive mode regulation

-

690

-

ns

Table 7.

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit