AS3900 datasheet(32/59 Pages) AMSCO

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AS3900

Data Sheet - Detail ed Description

Table 28. Communication

Step

Master

Client

All Timers are enabled at the Master via the REG

0x01<7:0>. The Master starts the Wakeup procedure as

described in chapter 11.4.

When the wakeup call is finished the Master switches

automatically the FSK receiver on for 1sec. During this

listening time, the Clients transmit randomly their first data.

With the first data all timing information is exchanged and

stored in the master’s timing table in SREG 0x0C to 0x13.

The Client timer is enabled via the REG 0x01<0>. MCU writes the

data into the dbuf register REG 0x38 to 0x51 and the payload data

length to the dlen register REG 0x37<4:0> via SDI. This has to be

performed in the time window between the finish of the last

communication and before next.

The enabled timer starts the transmit sequence and the interrupt

txstart is set. When the ID is transmitted (at the start of transmit) the

synchronization pulse is sent to the timing unit to start the new time

interval (cycle time)

The timing system, dedicated to each client in the master’s

timing table, wakes up the FSK receiver from the Sleep

Mode before the expected receive time expires (with guard

time, all timer interrupts are active). The guard time

depends on the previous history of communication and is

adjusted automatically. The receive window is defined by

the dedicated bitrate and the payload data length dlen.

ACK

Master receives the data from the client; after the ID is

received it is compared with the ID of the expected client

(defined ID and timing unit). If the ID is matching the

synchronization pulse is given to the timing block to

perform the timing synchronization. The ID is shifted to the

id_new registers REG 0x34 to 0x36, data length is stored

in the dlen bits, REG 0x37<4:0> and data is shifted to the

dbuf register, REG 0x38 to 0x51. At the end of the data

packet the interrupt dat_rtx is generated. One 32kHz clock

cycle after the final data is received the master is switched

from the receive mode to the transmit mode in order to start

an ACK transmission. After the end of ACK transmission

the system is powered down (only timer units running). The

communication error counter (cesX) for the according

Client is cleared.

ACK

One 32kHz clock cycle after end of the data transmission the Client

switches to receive mode awaiting ACK. The wait duration is defined

by the datarate. After ACK is received the interrupt ack_rtx is set and

the IC is powered down. The next data communication is started

automatically with the next timer iteration. The communication runs

until the timer0 is cleared via the command CLEAR_TIMER0. The

communication error counter (ces0) is cleared

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