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CDP1852/3 데이터시트(PDF) 2 Page - Intersil Corporation |
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CDP1852/3 데이터시트(HTML) 2 Page - Intersil Corporation |
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2 / 7 page ![]() 2 Block Diagram of CDP1852/3 FIGURE 1. FIGURE 2. CDP1852/3 LOGIC DIAGRAM CSI/CSI† MODE CS2 CLOCK CLEAR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 3 5 7 9 16 18 20 22 1 13 2 11 14 DEVICE SELECT DECODE CONTROL LOGIC 23 SR/SR† 24 12 VDD VSS RESET CLOCK ENABLE THREE- STATE OUTPUT DRIVERS 8-BIT DATA REGISTER 4 6 8 10 15 17 19 21 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 CSI SR CSI SR P1 P23 MODE = 0 MODE = 1 † POLARITY DEPENDS ON MODE S D R CL Q SERVICE REQUEST LATCH P TG N P TG N DO0 21 4 P N VSS 23 VDD 6 DO1 DO7 22 5 11 14 2 1 13 3 D17 DI1 DI0 CLOCK CLEAR MODE CSI/CSI CS2 VSS SR/SR CDP1852/3, CDP1852C/3 |
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