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CDP1852CD3 데이터시트(PDF) 7 Page - Intersil Corporation

부품명 CDP1852CD3
상세설명  High-Reliability Byte-Wide Input/Output Port
PDF  7 Pages
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1852CD3 데이터시트(HTML) 7 Page - Intersil Corporation

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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
NOTES:
1. CS1
• CS2 is the overlap of the CS1 = 0 and CS2 = 1.
2. Write is the overlap of CS1
• CS2 and clock.
MODE = 1 TRUTH TABLE
SERVICE REQUEST
TRUTH TABLE
CLOCK
CS1
• CS2 (NOTE 1)CLEAR
DATA OUT EQUALS
0X
0
0
CS1
or
CS2
Clock
• (CS1 • CS2)
or
CLEAR = 0
0
X
1
Data Latch
X
0
1
Data Latch
1
1
X
Data In
SR = 1
SR = 0
NOTE:
1. CS1
• CS2 = CS1 = 0, CS2 = 1
FIGURE 4. MODE = 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
CS1
• CS2
CLOCK
DATA IN
DATA OUT
SR
CLEAR
tSH
tCSR
(NOTE 1)
tRDO
tRSR
tCLR
tWDO
tDDO
tDS
tDH
tWW
tSSR
tCLK
(NOTE 2)
CDP1852/3, CDP1852C/3



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