CDCE6214RGET datasheet(22/53 Pages) TI1

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fSSC_MOD

fnom

fupper

flower

Freque ncy

Time

± fSPRE AD

fSSC_MOD

fnom

fupper =

flower

Freque ncy

Time

fSPRE AD

Down-Spr ead

Center-Spr ead

CDCE6214

SNAS811 – JULY 2020

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Product Folder Links: CDCE6214

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(1)

X signifies that this bitfield can take any value

(2)

For any other SSC spread and modulation rate, please contact TI representative.

The sigma delta modulator supports different order of MASH to shape the quantization noise. For Integer mode,

R27[1:0] is set as 0h. For fractional mode, it can be set to 1h, 2h or 3h for first, second and third order,

respectively.

In integer mode, PLL is configured in single-ended PFD configuration by setting R51[6]=1h. In Fractional mode,

PLL should be configured in Differential PFD configuration by setting R51[6]=0h. Further, R51[10] is set as 1h in

fractional mode and 0h in Integer mode.

9.3.2.2 Spread Spectrum Clocking

The energy of the harmonics from the rectangular clock signal can be spread over a certain frequency range.

This frequency deviation leads to lowered average amplitude of the harmonics. This can help to mitigate

electromagnetic interference (EMI) challenges in a system when the receiver supports this mode of operation.

The modulation shape is triangular.

The SSC clock is generated through the fractional-N PLL. When SSC is enabled, SSC clock is available on all

clock sourced from the PLL. Reference clock or PFD clock is available on the OUT1–OUT4 pins.

Down spread and center spread are supported. The following modes are supported.

•

PFD frequencies: Either 25 MHz or 50 MHz.

•

Down spread: –0.25% and ±0.5%

•

Center spread: ±0.25% and ±0.5%

Pre-configured settings are available to select any of these combinations.

Using these pre-configured settings, fmod of 31.5 kHz is synthesized for 100-MHz output clock.

Figure 25. Spread Spectrum Clock

Table 5. Spread Spectrum Settings (1) (2)

R41[15] - SSC_EN

R42[5] - SSC_TYPE

R42[3:1] - SSC_SEL

DESCRIPTION

No SSC modulation at output

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