INA821 datasheet(32/45 Pages) TI1

32 / 45 page

INA821

SBOS893D – AUGUST 2018 – REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

Submit Documentation Feedback

10 Power Supply Recommendations

The nominal performance of the INA821 is specified with a supply voltage of ±15 V and midsupply reference

voltage. The device also operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply

reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and

reference voltage are shown in the Typical Characteristics section.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

•

Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals. Even slight mismatch in parasitic capacitance at the gain

setting pins can degrade CMRR over frequency. For example, in applications that implement gain switching

using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch

capacitance is as small as possible and most importantly so that capacitance mismatch between the RG pins

is minimized.

•

Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in Figure 75, keep RG close to

the pins to minimize parasitic capacitance.

•

Keep the traces as short as possible.

•

Connect exposed thermal pad to negative supply –V.

INA821 데이터시트(PDF) 32 Page - Texas Instruments