XRT7250 datasheet(197/463 Pages) EXAR

197 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

178

Table 33 relates the content of this bit-field to the Bi-

polar Line Code that DS3 Data will be transmitted and

received at.

NOTES:

1. This bit is ignored if the Unipolar mode is selected.

2. This selection also effects the operation of the

Receive DS3 LIU Interface block

4.2.5.2

TxLineClk Clock Edge Selection

The Framer also allows the user to specify whether

the DS3 output data (via TxPOS and/or TxNEG out-

put pins) is to be updated on the rising or falling edg-

es of the TxLineClk signal. The purpose of this fea-

ture is to insure that the Framer will always be able to

output data to the LIU IC, in such a way that the LIU

set-up and hold time requirements can always be

met. This selection is made by writing to bit 2 of the I/

O Control Register, as depicted below.

Table 34 relates the contents of this bit field to the

clock edge of TxClk that DS3 Data is output on the

TxPOS and/or TxNEG output pins.

NOTE: The user will typically make the selection based

upon the set-up and hold time requirements of the Transmit

LIU IC.

I/O CONTROL REGISTER (ADDRESS = 0X01)

BIT 7BIT 6BIT 5

BIT 4BIT 3BIT2BIT 1BIT 0

Disable TxLOC

LOC

Disable

RxLOC

AMI/ZeroSup*

Unipolar/

Bipolar*

TxLine CLK

Invert

RxLine CLK

Invert

Reframe

R/W

R/WR/W

R/W

000

TABLE 33: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR

LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK

BIT 4BIPOLAR LINE CODE

B3ZS

1AMI

II/O CONTROL REGISTER (ADDRESS = 0X01)

BIT 7BIT 6BIT 5BIT 4BIT 3

BIT2BIT 1BIT 0

Disable TxLOC

LOC

Disable

RxLOC

AMI/ZeroSup*

Unipolar/

Bipolar*

TxLine CLK

Invert

RxLine CLK

Invert

Reframe

R/W

100

TABLE 34: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL

BIT 2RESULT

Rising Edge:

Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.

See Figure 70 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.

Falling Edge:

Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.

See Figure 71 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.

XRT7250 데이터시트(PDF) 197 Page - Exar Corporation

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