XRT7250 datasheet(206/463 Pages) EXAR

206 / 463 page

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

187

Table 36 depicts the relationship between the value of

this bit-field to the sampling clock edge of RxLineClk.

Figure 78 and Figure 79 present the Waveform and

Timing Relationships between RxLineClk, RxPOS

and RxNEG for each of these configurations.

II/O CONTROL REGISTER (ADDRESS = 0X01)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT2

BIT 1BIT 0

Disable

TxLOC

LOC

Disable

RxLOC

AMI/ZeroSup*

Unipolar/

Bipolar*

TxLine CLK

Invert

RxLine CLK

Invert

Reframe

R/W

0100

TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER,

AND THE SAMPLING EDGE OF THE

RXLINECLK SIGNAL

RXCLKINV

(BIT 1)

RESULT

Rising Edge:

RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 78 for timing relationship

between RxLineClk, RxPOS, and RxNEG.

Falling Edge:

RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 79 for timing relationship

between RxLineClk, RxPOS, and RxNEG.

FIGURE 78. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND

RXNEG ARE TO BE SAMPLED ON THE RISING EDGE OF RXLINECLK

RxLineClk

RxPOS

RxNEG

t38

t39

t42

XRT7250 데이터시트(PDF) 206 Page - Exar Corporation

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