FPD750DFN datasheet(3/5 Pages) FILTRONIC

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FPD750DFN

LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT

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BIASING GUIDELINES

Active bias circuits provide good performance stabilization over variations of operating

temperature, but require a larger number of components compared to self-bias or dual-biased.

Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,

otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for

additional information.

Dual-bias circuits are relatively simple to implement, but will require a regulated negative

voltage supply for depletion-mode devices such as the FPD750DFN.

For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of

RF gain expansion prior to the onset of compression is normal for this operating point. Note that

pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at

50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%

to 33% of IDSS range is suggested.

Such Class AB operation will not degrade the IP3

performance.

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PACKAGE OUTLINE (dimensions in mm)

All information and specifications subject to change without notice.

Phone: +1 408 850-5790

http://www.filtronic.co.uk/semis

Revised: 11/14/05

Fax: +1 408 850-5766

Email: sales@filcsi.com

FPD750DFN 데이터시트(PDF) 3 Page - Filtronic Compound Semiconductors