STV7612 datasheet(13/18 Pages) STMICROELECTRONICS

13 / 18 page

STV7612

ADCS 7399251

13/18

AC TIMINGS REQUIREMENTS

(VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns)

AC TIMINGS CHARACTERISTICS

(VCC = 5 V, VPP = 90 V, VSPP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C)

(VIL(Max.) = 0.2 Vcc, VIH(Min.) =0.8 VCC, VOH = 4.0V, VOL = 0.4 V, unless otherwise specified)

Note 7 For IC in cascading configuration and in case a time delay is inserted on the clock signal of the cascaded IC, the

maximum value of this time delay must be set at the minimum value of tPHL1, tPLH1 (Figure 7).

Note 8 One output among 96, loading capacitor CL = 50pF, other outputs at low level.

Symbol

Parameter

Min.

Typ.

Max.

Unit

tWHCLK

Duration of clock (CLK) pulse at high level

tWLCLK

Duration of clock (CLK) pulse at low level

tSDAT

Set-up Time of data input before clock (low to high) transition

tHDAT

Hold Time of data input after clock (low to high) transition

tSFR

F/R (FOR/REV) Set-up Time before clock (low to high) transition

100

tDSTB

Minimum Delay to latch STB after clock (low to high) transition

tSSTB

Minimum Delay to latch STB before clock (low to high) transition

tSTB

Latch STB Low Level Pulse Duration

tBLK

Blanking BLK Pulse Duration

500

tPOL

Polarity POL Pulse Duration

500

Symbol

Parameter

Min.

Typ. Max. Unit

tCLK

Data clock Period

tRDAT

Logical Data Output Rise Time (CL=10pF)

tFDAT

Logical Data Output Fall Time (CL=10pF)

tPHL1

tPLH1

Delay of logic data output (high to low transition) after clock (CLK) transition Note 7

Delay of logic data output (low to high transition) after clock (CLK) transition Note 7

tPHL2

tPLH2

Delay of power output change (high to low transition) after clock (CLK) transition

Delay of power output change (low to high transition) after clock (CLK) transition

135

180

tPHL3

tPLH3

Delay of power output change (high to low transition) after Latch (STB) transition

Delay of power output change (low to high transition) after Latch (STB) transition

115

165

tPHL4

tPLH4

Delay of power output change (high to low transition) to Blank or Polarity (BLK, POL)

transition

Delay of power output change (low to high transition) to Blank or Polarity (BLK, POL)

transition

100

160

tROUT

Power Output Rise Time ( Note 8)

150

tFOUT

Power Output Fall Time ( Note 8)

200

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