STV7612SLASHWAF datasheet(10/18 Pages) STMICROELECTRONICS

10 / 18 page

STV7612

10/18

ADCS 7399251

CIRCUIT DESCRIPTION

The STV7612 contains all the logic and the power

circuits necessary to drive the columns of a Plas-

ma Display Panel (P. D. P.). The binary value of

each pixel of the displayed line is loaded into the

shift register. Data are input in a 6-bit wide data

bus to A1 - A6 input (case of forward shift mode).

Data are shifted at each low to high transition of

the CLK shift clock. After 16 shifts the first data are

available on B1 - B6 outputs. These B1 - B6 out-

puts can be used to cascade several drivers to

perform any horizontal resolution. The forward/re-

verse

(F/R) input is used to select the direction of

the shift register, A1 - A6 and B1 - B6 data bus in-

put/output status is set according to the selected

direction. F/R= H, A is an input and B is an output.

Serial inputs, CLK, STB inputs are Smith trigger in-

puts. If not used in the application, Blanking (BLK),

Polarity (POL are internally pulled to level “H”. The

maximum frequency of the shift clock is 20 MHz.

This leads to an equivalent 120 MHz serial shift

On low level of STB, data is transferred from shift

freshed as long as STB is kept high.

Blanking input (BLK) forces the power outputs to

low level when pulled low. All the power outputs

are set at high level when the Polarity command

(POL) is pulled low and the Blanking (BLK) input is

at high level.

VSSSUB and VSSLOG must be connected as close

as possible to the logical reference ground of the

application.

Shift Register Truth Table

Power Output Truth Table

Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 =

A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90]

Input

Input/Output

Shift Register

Function

F/R

CLK

Output Q

Rise

OUT

Forward shift

H or L

OUT

Steady

Rise

OUT

Reverse shift

H or L

OUT

Steady

STB

BLK

POL

Driver

Output

Comments

Output low

Output high

Data latched

Data copied

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