GPIO6 datasheet(48/60 Pages) MICROCHIP

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USB5806

DS00002236D-page 48

 2016-2018 Microchip Technology Inc.

9.6.2

POWER-ON AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where

RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following

timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in

Section 9.2, Operating Conditions**.

Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Con-

figuration Strap Timing for additional details.

9.6.3

RESET AND CONFIGURATION STRAP TIMING

Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of

RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to

Section 8.4, Resets for additional information on resets. Refer to Section 3.5, Configuration Straps and Programmable

Functions for additional information on configuration straps.

FIGURE 9-3:

POWER-ON CONFIGURATION STRAP VALID TIMING

TABLE 9-6:

POWER-ON CONFIGURATION STRAP LATCHING TIMING

Symbol

Description

Min

Typ

Max

Units

tcsh

Configuration strap hold after external power supplies at opera-

tional levels

1ms

FIGURE 9-4:

RESET_N CONFIGURATION STRAP TIMING

TABLE 9-7:

RESET_N CONFIGURATION STRAP TIMING

Symbol

Description

Min

Typ

Max

Units

trstia

RESET_N input assertion time

s

tcsh

Configuration strap pins hold after RESET_N deassertion

Note:

The clock input must be stable prior to RESET_N deassertion.

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.

All External

Power Supplies

Vopp

Configuration

Straps

RESET_N

Configuration

Straps

trstia

tcsh

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