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AS7C331MNTD32A-166TQC 데이터시트(PDF) 1 Page - Alliance Semiconductor Corporation

부품명 AS7C331MNTD32A-166TQC
상세설명  3.3V 1M x 32/36 Pipelined SRAM with NTD
PDF  18 Pages
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제조업체  ALSC [Alliance Semiconductor Corporation]
홈페이지  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

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December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MNTD32A
AS7C331MNTD36A
12/23/04, V 1.6
Alliance Semiconductor
P. 1 of 18
3.3V 1M × 32/36 Pipelined SRAM with NTDTM
Features
• Organization: 1,048,576 words × 32 or 36 bits
•NTD™architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-200
-166
-133
Units
Minimum cycle time
5
6
7.5
ns
Maximum clock frequency
200
166
133
MHz
Maximum clock access time
3.2
3.5
3.8
ns
Maximum operating current
450
400
350
mA
Maximum standby current
170
150
140
mA
Maximum CMOS standby current (DC)
90
90
90
mA
Address
D
Q
CLK
register
Output
Register
DQ[a,b,c,d]
20
20
CLK
CE0
CE1
CE2
A[19:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
32/36
32/36
OE
1M x 32/36
SRAM
Array
R/W
DQ[a,b,c,d]
BWb
BWd
CLK
Q
D
ADV / LD
LBO
Burst logic
addr. registers
Write delay
20
ZZ
CLK
32/36
32/36
32/36
32/36
BWc
BWa


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